1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of fabricating a semiconductor device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for fabricating a semiconductor device having a local interconnection (LI) between a gate and a junction.
2. Discussion of the Related Art
FIGS. 1A to 1C are cross-sectional views illustrating the process steps of fabricating a semiconductor device according to a related background art.
Initially referring to FIG. 1A, a P well 21 and an N well 22 which have a predetermined depth are formed in a semiconductor substrate 11. A thin silicon oxide (SiO.sub.2) layer is formed on the exposed surface of the semiconductor substrate 11 which has an isolation layer 13 selectively formed to define an active region. A thick polysilicon layer is then deposited on the thin silicon oxide layer as well as on the isolation layer 13. Using a photolithographic process, a photoresist film (not shown) is formed on the polysilicon layer formed at a gate region. In this process, the photoresist film acts as a mask, and a portion of the polysilicon layer is removed by a plasma etching method. Thus, first, second, third, and fourth gates 37a, 37b, 37c, and 37d are formed on the semiconductor substrate 11, and only portions 23a and 23b of the silicon oxide layer remain below the first and second gates 37a and 37b. After the first to fourth gates 37a to 37d are formed, the photoresist film is removed from each gate.
Thereafter, using photolithography, the N well region 22 is covered with a photoresist film (not shown) while the P well region 21 is exposed. The first gate 37a is used as a mask, so that a self-alignment process is used in executing an ion implantation to form a lightly doped drain (LDD) region in the semiconductor substrate of the P well region 21. Thus, a lightly doped N-type region 40 is formed at both sides of the first gate 37a in the semiconductor substrate.
Similarly, after removing the photoresist film, only the N well region 22 is exposed by photolithographic process. The second gate 37b is then used as a mask to form a lightly doped P-type region 41 of the N well region 22 by an ion implantation. Thus, the lightly doped P-type region 41 is formed at both sides of the second gate 37b in the semiconductor substrate by a self-alignment process.
The isolation layer 13 is formed of a silicon oxide (SiO.sub.2) layer formed by a shallow trench isolation (STI) method. The above-mentioned thin silicon oxide film is grown on the semiconductor substrate 11 by thermal oxidation. The first, second, third, and fourth gates 37a, 37b, 37c, and 37d are polysilicon layers having a thickness of in the range of 2500 to 4000 .ANG.. Also, the polysilicon layers have a fine grain structure and are deposited by chemical vapor deposition (CVD).
The first and second gates 37a and 37b protect the respective the silicon oxide (SiO.sub.2) layers 23a and 23b from a channeling effect during the subsequent ion implantation. The photoresist film is removed using a solvent or oxygen plasma.
In the process of forming the lightly doped N-type region 40, ion implantation is performed with phosphorus (P) ions of 1.0.times.10.sup.13 to 1.0.times.10.sup.14 atoms/cm.sup.2 using an acceleration energy of 40 KeV. Simultaneously, the first and third gates 37a and 37c are also lightly doped by ion implantation. In forming the lightly doped P-type region 41, (using BF.sub.2 as a boron source) ion implantation is performed with boron ions of 1.0.times.10.sup.13 to 1.0.times.10.sup.14 atoms/cm.sup.2 using an acceleration energy of 50 KeV. Similarly, the second and fourth gates 37b and 37d are lightly doped by ion implantation.
Referring to FIG. 1B, a silicon oxide (SiO.sub.2) layer is deposited on the entire surface of the semiconductor substrate 11 by CVD. Then, silicon oxide layer is etched by anisotropic plasma etching to form a plurality of spacers 43 on sides of the gates 37a, 37b, 37c, and 37d.
Subsequently, a photolithography is performed to cover the N well region 22 with a photoresist film (not shown) and to expose the P well region 21. The first gate 37a is used as a mask in performing an N-type ion implantation in the semiconductor substrate of the P well region 21. Thus, a self-alignment process is used in forming a heavily doped N-type region 45. Similarly, a heavily doped P-type region 47 is formed by using the second gate 37b as a mask for performing a P-type ion implantation. In this process, the photoresist film (not shown) covers only the P well region 21, so that the N well region 22 is exposed for the process.
Thereafter, the semiconductor substrate 11 is subjected by annealing at the temperature in the range of 900 to 950.degree. C. to form source regions 41 and 47 of PMOS and drain regions 40 and 45 of NMOS, which have predetermined junction depths.
In forming the spacers 43, the silicon oxide layer formed by a CVD method is etched by an anisotropic plasma etching process using a gas such as He, C.sub.2 H.sub.6 and CHF.sub.3.
In the step of forming the heavily doped N-type region 45, ion implantation is performed with As ions of 5.0.times.10.sup.15 atoms/cm.sup.2 using an acceleration energy of 100 KeV. At the same time, the first and third gates 37a and 37c are heavily doped by ion implantation. Similarly, the heavily doped P-type region 47 is formed by ion-implanting boron ions of 3.0.times.10.sup.15 atoms/cm.sup.2 using an acceleration energy of 50 KeV. Simultaneously, the second and fourth gates 37b and 37d are heavily doped by ion implantation.
AS shown in FIG. 1C, CoSi.sub.2 layers 49a and 49b are formed on the source and drain regions 47 and 45 and on the upper surface of the first, second, third, and fourth gates 37a, 37b, 37c, and 37d by high temperature sputtering and in-situ vacuum annealing methods. Then, a thin silicon nitride (Si.sub.3 N.sub.4) layer (not shown) and a thick borophosphosilicate glass (BPSG) layer 51 are deposited on the entire surface of the semiconductor substrate 11 by CVD. The BPSG layer is removed to have a predetermined thickness by chemical-mechanical polishing (CMP), so that the surface of the BPSG layer 51 is planarized. Using a photoresist film (not shown) as a mask, a predetermine portion where photoresist film is not covered is removed by plasma etching. Thus, this process removes a portion of the CoSi.sub.2 layer 49a on the source and drain regions 47 and 45 and a portion of the spacers 43, and the isolation layer 13 of the third and fourth gates 37c and 37d. The photoresist film is then removed from the gates.
A thin titanium (Ti)/titanium nitride (TiN) film (not shown) and a thick tungsten (W) layer 53 are deposited on the entire surface of the semiconductor substrate 11 by a sputtering method. A portion of the multi-layers (W/TiN/Ti) deposited on the BPSG layer are removed completely by a CMP method. Thus, a portion of the layers (W/TiN/Ti) remain only in a predetermined groove-type portion. As a result, the layers 53 acts as a local interconnection (LI) between the gate and junction.
In the above-described process, the CoSi.sub.2 layer is formed of a 150 .ANG. thick salicide layer which is converted from a cobalt film deposited by a sputtering method in a salicide process. The silicon nitride layer Si.sub.3 N.sub.4 is deposited to have a thickness in the range of 500 to 1000 .ANG. by CVD. The BPSG layer is deposited to have a thickness of 8000 to 10000 .ANG. using CVD. The Ti layer is formed to have a thickness in the range of 200 to 400 .ANG. by sputtering. The W layer is deposited to have a thickness of 4000 to 5500 .ANG. by sputtering.
However, the above-described related background art has a serious drawback. For example, the fabrication process becomes very complicated and takes much time. In forming a local interconnection between a gate and a junction, a main problem of the background art method is caused by the process steps of etching inter-level dielectric layers to expose the gate and the junction.